1. Field of the Invention
The present invention relates to a technique for forming custom logic integrated circuits utilizing CMOS cell arrays and, more particularly, to the utilization of a transistor isolation technique, in lieu of field oxide isolation, to combine the advantages of the gate array and standard cell design processes.
2. Description of the Prior Art
In designing custom logic circuits, which often include many thousands of separate devices, automated design and layout techniques must be utilized which provide quick turnaround time to avoid spending many valuable hours attempting to manually produce a workable and efficient logic circuit design. There are two popular approaches in the prior art to providing this quick turnaround, standard cell (polycell) design and gate array design.
Integrated circuits designed with polycells, or pre-characterized groups of transistors capable of performing a specific function, offer a great deal of flexibility in terms of final circuit function. One such design arrangement is discussed in the article "16b CPU Design by a Hierarchical Polycell Approach" by T. Tokuda et al, appearing in the Proceedings of the IEEE International Conference on Circuits and Components (ICCC 82), September 28-October 1, 1982, at pp. 102-5. The standard cell approach offers a rich library of functions, or precharacterized cells, allowing the designer to create virtually any logic circuit desired. A drawback of this approach, however, is that since each polycell definition contains all of the mask level for the entire logic circuit and it is impossible to predict where the various geometries on the different mask levels will finally be placed, it is necessary to respecify all mask levels for each new circuit and accordingly have to wait for all these levels to be processed for initial circuit evaluation. It is not unusual for a custom logic circuit to require ten or more mask levels, thus requiring an extended processing interval.
The gate array concept of circuit design addresses this long processing turnaround problem by having, on partially preprocessed wafers, predefined circuit elements which are isolated from one another by a thick oxide region and only require interconnection processing steps to form the completed circuit. Hence, in this case a designer needs only to specify the interconnection of these preplaced transistors or groups of transistors to implement a given LSI circuit design. As the transistor placement is known, silicon wafers containing these transistors can be preprocessed up to but excluding the interconnection mask levels. The few remaining mask levels (typically two to four levels) necessary for interconnection will then be processed to implement a specific function. A complete description of an exemplary gate array design technique can be found in the article "CMOS Gate Arrays: Design Techniques and Tradeoffs" by M. Insley et al appearing in the Proceedings of the 1982 Custom Intergrated Circuits Conference, May 17-19, 1982 at pp. 304-6. The gate array technique, however, is inherently limited to designing with partially preprocessed wafers, restricting the number of functions for the designer to chose from and thereby limiting the amount of customizing the designer may do.
One technique for increasing the customization possible with gate arrays is discussed in the article "A CMOS/SOS Gate Array with a New Customization Technique of Cutting" by N. Sasaki et al appearing in IEEE Transactions on Electron Devices, Vol. ED-29, No. 10, October 1982 at pp. 1535-1541. As discussed by the authors, customization of the silicon wiring level is realized by arbitrarily cutting the pre-defined epitaxial-silicon lines into many pieces after the fabrication of the transistors. Customization at the silicon wiring level results in higher packing density and reduction of the silicon wiring channels by a factor of two. Another problem with gate arrays, however, is that the thick field oxide regions, which separate the transistor pairs forming the basic circuit elements, occupy a large portion of the gate array structure. This factor appreciably reduces the number of actual circuit elements which may be included in the complete logic circuit. One solution to this problem is to utilize "gate isolation" in place of the field oxide regions to separate the circuits. This concept is discussed in detail in an article entitled "Gate Isolation-A Novel Basic Cell Configuration for CMOS Gate Arrays" by I. Ohkura et al appearing in Proceedings of the 1982 Custom Integrated Circuits Conference, May 17-19, 1982 at pp. 307-310. In particular, the gate isolation method proposes forming the basic CMOS cell out of a single transistor pair, where the transistor pairs are arranged in a row, closely spaced, without oxide isolation, resulting in a serial p-channel transistor chain and a serial n-channel transistor chain. A master slice gate array formed by this method is discussed in the article "A 10K Gate CMOS Gate Array with Gate Isolation Configuration" by K. Sakashita et al appearing in Proceedings of the 1983 Custom Integrated Circuits Conference, May 23-25, 1983 at pp. 14-18. A problem with this gate isolation approach, however, is that many standard cell definitions require at least two or three n- and p-channel transistor pairs and, therefore, cannot be utilized since the gate isolation standard cell contains only one transistor pair. Further, many more interconnections between cells are necessary in this configuration than are needed in custom logic circuits formed by the prior art methods discussed above.
Thus, there remains to desire to provide a method of achieving custom logic integrated circuit design which can provide quick turnaround time without the disadvantages of thick field oxide isolation or cell definition restrictions related to the above-cited methods.